Method of etching porous dielectric

ABSTRACT

The present invention relates to methods of etching a porous dielectric. The method includes etching the film in a plasma etch chamber with CF 4 , H 2  and a noble gas, wherein the CF 4  to H 2  gas flow ratio is between 1.33:1 and 2.7:1 and the noble gas is greater than about 42% of the total gas flow to the plasma chamber.

CROSS-REFERENCE TO RELATED APPLICATIONS

A claim of priority is made to U.S. provisional application Ser. No.60/468,263, filed May 7, 2003, and to British patent application no.0310238.1, filed May 3, 2003.

BACKGROUND OF THE INVENTION

The present invention relates to methods of etching a porous dielectriclayer that forms part of an interconnect structure on a substrate suchas a wafer or multi chip module. In particular, but not exclusively, itrelates to a method of etching a porous dielectric layer forming part ofa dual damascene structure. More particularly it relates to a method ofetching the upper part of a dual damascene structure.

To reduce the RC product in interconnect layers there is a requirementto reduce the capacitive coupling between adjoining conductors. Lowdielectric constant (k) materials are therefore desirable and it isknown that a vacuum gap has the lowest k value of 1. A known method ofreducing bulk insulators' k values is to introduce porosity such thatthere is a matrix material and voids, thereby reducing the k value toless than that of the matrix.

Such porous materials present numerous problems for integration intopractical devices and an additional complexity is introduced by therequirement to make ever smaller structures. As yet no porousdielectrics have been successfully integrated into state of the artdevices in volume manufacturing for public sale.

At e.g. the 65 nm technology node there is a potential integrationscheme whereby the total thickness of the dual damascene dielectric isdeposited without an etch stop layer within it. The trench is thenetched for a timed period into the dielectric and the etching terminatedpart way through the thickness of the dielectric. Over and above all thewell known desirable aspects of anisotropic etching there is anadditional requirement that the base of the etched trench is smooth. Ifthe dielectric is porous (i.e. containing voids) then this is clearly achallenge. If the voids are very small then stopping in the voideddielectric may be acceptable though some degree of ‘healing’ of thesevoids is also desirable.

The Applicants have developed a porous dielectric known as Orion™ as isdescribed in various patent applications in the name of the Applicants,e.g. WO/03/009364. This material has a k value in the range of 1.8 to2.6 and is under evaluation at this time for integration into 65 nm (andbelow 65 nm) design rule logic devices at a k value of 2.2 to 2.5. It isthis material that has been etched in this invention, though theinvention also relates to any porous carbon doped silicon dioxide low-kdielectric e.g. a SiCOH type material. Typically such carbon dopedoxides have methyl groups contained within them. Carbon (and therebyhydrogen) concentrations may be varied, higher concentrations leading toporosity under certain circumstances.

It should be made clear that this application is not related to theetched sidewalls. It is well known that to achieve anisotropic(directional) etching polymer is deposited on sidewalls to protect themfrom chemical attack whilst bombardment of the etch front (base oftrench) removes this protective layer enabling downward etching. Afteretching the photoresist and any remaining polymer is then removed.

It should also be understood that in almost all cases layers of materialforming interconnect layers are completely etched through such that theetch process stops on an ‘etch stop’ layer or some other layer thatetches more slowly in the etchant than the layer being etched. It issomewhat unusual to terminate an etch part way through a layer butelimination of a device etch-stop layer is highly desirable as itreduces the effective k value of the structure and reduces the number ofinterfaces between layers. The Applicants have found (in unpublishedwork) that, perhaps not surprisingly, when such a partial etch isperformed on a porous dielectric then a rough trench base is formed.This can be seen in FIGS. 1 (a) and 1 (b).

FIG. 1 (a) and (b) show rough etch front on SEM images after partialetch using CF₄ and CH₂F₂ gases, at 1250 W helicon source plasma power,400 W platen (wafer) bias power, 2 mTorr, with wafer helium backpressure of 15 Torr (giving a wafer surface temperature of approximately90-100° C. as indicated by temperature sensitive labels) in a MORI™process chamber, as supplied by the Applicants.

FIG. 1 (a) shows a dual damascene structure. The etched porous oxidesurface is at 1.

There is therefore a need for an improved etch process to provide asmooth base to an etched feature formed within a carbon doped siliconoxide type porous dielectric layer.

SUMMARY OF THE INVENTION

From one aspect the invention consists in a method of etching a porouscarbon-doped silicon dioxide type dielectric film including plasmaetching the film in a plasma etch chamber with CF₄H₂ and a noble gas,wherein the CF₄ to H₂ gas flow ratio is between 1.33:1 and 2.7:1 and thenoble gas is greater than about 42% of the total gas flow to the plasmachamber.

From another aspect the invention provides a method of plasma etching aporous dielectric layer of carbon doped silicon oxide material such as aSiCOH material with the following desirable characteristics:Characteristic Target result Etch depth 40-70% of film thickness Etchrate 200-500 nm/min Selectivity to photoresist Greater than 5:1 ARDEpercentage less than 5% (Aspect Ratio Dependent Etch rate: thedifference in etch rate in features of different aspect ratio) Side wallangle 90 degrees Micro-trenching none visible in an electron micrographRoughness none visible in an electron micrograph when surface viewed inplan view or at 45° degree glancing angle (at minimum magnification of20,000)

Although the invention has been defined above it includes any inventivecombination of the features set out above or in the followingdescription.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be performed in various ways and specific embodimentswill now be described with reference to the accompanying drawings:

FIGS. 1(a) and (b), are SEM images of an etch front and partial etchusing CF₄ and CH₂F₂ gases;

FIGS. 2(a), (b) and (c) illustrate similar etch fronts using CF₄ and H₂with increasing amounts of argon present;

FIG. 3(a)a shows the etch front resulting from a non optimised process,whilst FIG. 3(b) illustrates the effect of a partial oxygen based resiststep on the material of 3 (a);

FIGS. 4(a), (b) and (c) illustrate the effect of reducing amounts ofbackside cooling whilst FIGS. 5(a) and 5(b) are similar SEM's for aspecified set of process conditions;

FIGS. 6(a) and (b) illustrate the results of the process using reducedcooling for particular process conditions and can be compared with FIG.7 where the same process was run, but with increased cooling; and

FIGS. 8(a) and (b) show the etch front surfaces before and after resistetch has taken place.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Whilst a rough etch front 1(a) and (b) exhibited in FIG. 5 might bethought of as an obvious consequence of the film's porosity, it wasobserved that the surface roughness was greater than the mean pore sizeof 1-4 nm. This therefore suggested that the roughness of the etch frontwas not simply the result of exposure of pores and it was thereforepostulated that an improved etch process could yield a smoother etchfront/base of trench.

Initially the Applicants determined that noble gas additions, such asargon improved the smoothness of the etch front as illustrated in FIGS.2, a, b and c.

Each of the processes illustrated in FIG. 2 was carried out in the MORI™chamber referred to above with the chamber pressure being 110 mT, theplasma power 700 w applied to the wafer platen only and wafer heliumbackside pressure of 15 T (i.e. the water temperature was approximately90-100° C.).

The gas flow rates, in seem, for the samples illustrated in FIGS. 2(a),(b) and (c) respectively were as follows: CF₄ 80 60 60 H₂ 30 30 30 Ar 090 120

At 1 can be seen the etch front/base surface of the porous oxide wherea) is no argon additions, b) has argon added, and c) has the most argonadded to a reactive ion etch process of CF₄+H₂. It will be seen that theaddition of argon results in a smoother etch front 1, with that of 2(c)being the smoothest. This is contrary to expectation, as it would beanticipated that increasing the physical sputter etch component byadding a heavy noble gas would increase roughness of etch front of amaterial of non-uniform density.

The process of FIG. 2 c is still not acceptable and shows for examplepronounced microtrenching at 2.

It will be noted that in all cases the Applicants had selected a CF₄ andH₂ mix, rather than the more usual CF₄/O₂ for the etch gas for thefollowing reasons.

CF₄ is a well known and readily available fluorine source and can etchwith lower wafer bias power levels than other well known fluorinecontaining etch gasses because of its low polymer generation. Whilstsilicon dioxide films are generally etched in a CF₄+Oxygen gas mix itwas determined that oxygen should be excluded from the etch process,because the Applicants anticipated that there may be methyl groupsformed in the film, which would be stripped from the film by O₂.

Hydrogen was then selected as an additional process gas on the basis ofits ability to scavenge fluorine and increase selectivity by depressingthe etch rate of silicon compared to silicon dioxide or carbide.Hydrogen plasma is known to cure or treat low-k materials fromApplicants GB-A-0020 509. Increasing levels of hydrogen are known tohave only a limited effect on silicon dioxide etch rate and to increasepolymerization. Therefore the plasma would provide hydrogen radicalsfrom hydrogen gas directly, rather than from CH₂F₂ gas.

Argon was selected as a heavy noble gas (others may have been selected,such as krypton or xenon) because of its ability to increase ionizationefficiency.

Considerable DOE (Design of Experiment) experimentation was thenperformed yielding the conclusions that a CF₄:H₂ ratio of 2:1 was thebest for this application, and a range of CF₄ to H₂ gas flow ratios ofbetween 1.33:1 and 2.7:1 were acceptable.

This is an unusually high hydrogen concentration. It is generally heldthat in a CF₄+Hydrogen gas mix, the etch rate of both silicon dioxideand silicon falls to about zero at about 40% hydrogen in the CF₄+H₂ gasmix due to the level of polymerization.

It was further discovered that for the CF₄ and H₂ flows rates beingused, the argon flow should be at least 90 sccm and preferably about 77percent of total gas flow. In a process of 80 sccm CF₄ and 40 sccm ofhydrogen, then argon gas flow was preferably 400 sccm and at least 90sccm.

A further non-optimized process is shown at FIG. 3 a. At 1 the etchfront can be seen and shows some surface roughness e.g. at 4 and microtrenching e.g. at 2 after etch completion into approximately 80 percentof Orion porous SICOH material with a k value of 2.2. ARDE is less than2% (0.25 nanometres /1.25 micron structures), selectivity to photoresist3 is greater than 6:1 and the etch rate is greater than 300 nm/min. Thesame structure as at FIG. 3 a was then subjected to a partial oxygenbased resist strip and the results are shown at FIG. 3 b. As can be seenthere is severe roughening of the etched base of the trench.

It has been discovered that to further improve etch results stoppingwithin the thickness of the porous carbon-doped oxide then two furthervariations are necessary. Firstly, the porous SICOH material should havesmall pores with tightly controlled distribution. A material withaverage pore sizes in the range 1-4 nm etches more smoothly that aporous dielectric with a larger average pore size e.g. 4-5 nm and poresranging in size from 2 nm-12 nm. It has also been found that the wafertemperature during etching has an effect on the surface roughness of theetch front.

Higher wafer temperatures yield smoother etch fronts. However, themaximum temperature is limited by photoresist reticulation.

It is notoriously difficult to specify the temperature of a film duringan etch (or deposition) process as it is practically impossible tomeasure. Attempts at estimation may be made using temperature indicatingstickers or ‘Sensarray™’ wafers with embedded thermocouples, but theseare only approximations. It has however been noted that reducing thepressure of helium to the backside of the electrostatically clampedwafer (thereby reducing the thermal coupling of the wafer to the chilledelectrostatic chuck) improved etch front smoothness as illustrated inFIGS. 4 a and b. These are submicron structures etched to 86% of theOrion film thickness both with the electrostatic chuck coolant set to−15° C. At FIG. 4 a is the etch result with 15 torr of helium pressure(sufficient to thermally couple the wafer to the chuck with a smallthermal gradient) and in the case of FIG. 4 b the helium pressure is 2torr. As can be seen the etch front 1 at FIG. 4 b is smoother than atFIG. 4 a.

Temperature sensing stickers on the face of a wafer indicate a wafersurface temperature of 93-99° C. for 15 torr pressure, −15° C. coolanttemperature, and 143-149° C. for 2 torr helium backpressure and −15° C.coolant temperature.

An acceptable wafer surface temperature for the process of thisinvention is therefore estimated as above 100° C., preferably within therange 130° C. to 220° C., more preferably between 130-170° C. and mostpreferably about 150° C. (the upper temperature limited by thephotoresist, higher temperatures being otherwise at least potentiallyequally preferable).

Minimum preferred pressure for the process is 80 mTorr. FIG. 5 (a) and(b) show the onset of etch front 1 surface roughness 4, for gas flows of70 sccm CF₄, 30 sccm H₂, 90 sccm Ar, 700 W, with a wafer helium backpressure of 15 T (wafer ‘cold’).

FIG. 6 (a) and (b) show smooth etch front 1 after etching at higherwafer surface temperature (130° to 170° C.). This is achieved byreducing the Helium back pressure to 2 Torr, thereby lowering thethermal coupling of platen to wafer. The process conditions whereotherwise revise CF₄—84 sccm; H₂—42 sccm; Ar—400 sccm; pressure 200 mland power 1000 W.

FIG. 7 shows rougher etch fronts after processing at lower wafer surfacetemperature (−10 to +99° C.), when Helium back pressure is 15 Torr. Herethe process conditions where essentially identical to those for FIG. 6with slight variations in the CF₄ and H₂ flow rates being 82.55 sccm and37.5 sccm respectively.

In order to prove that smooth etch front surface of the invention is notdue to polymer residues covering the etch front/base, a N₂+H₂ plasmastrip was used to remove the photoresist post-etch. FIG. 8 (a) shows thesmooth etch front 1 and photoresist 3 in place after hot etch. Figure 8(b) shows the equally smooth etch front surface 1 after N₂+H₂ plasmastrip to remove the photoresist. There is no visible polymer residueremaining.

The first order major responses of each individual factor can thus besummarized below. etch front increasing smoothness μ-trenching ARDE sidewall angle CF₄/H₂ ↓ ↓ ↑ — Ar Flow ↑ — ↓ — pressure — ↓ ↑ — power — ↑ ↓ ↑temperature ↑ ↓ — —

Best known process conditions to partially etch a porous SICOH typedielectric to leave a smooth etch front are therefore: Etch gasses: 80sccm CF₄, 40 sccm H₂, 400 sccm Ar, 5% variation in CF₄ and H₂ wouldyield similar result, so long as the CF₄:H₂ ratio is kept at about 2:1.Etch process pressure: 200 mTorr, Plasma power:1000 W: 13.56 MHz appliedto the wafer plate (RIE) (Power needs to be increased as pressureincreases to avoid “wafer lens effect”) wafer surface temp.: 100 to 170°C. (e.g. by adjusting platen temperature and/or Helium wafer backpressure thermal coupling)

1. A method of etching a porous carbon-doped silicon dioxide type dielectric film including plasma etching the film in a plasma etch chamber with CF₄, H₂ and a noble gas, wherein the CF₄ to H₂ gas flow ratio is between 1.33:1 and 2.7:1 and the noble gas is greater than about 42% of the total gas flow to the plasma chamber.
 2. A method as claimed in claim 1 wherein the CF₄:H₂ ratio is about 2:1.
 3. A method as claimed in claim 1 wherein the noble gas is argon.
 4. A method as claimed in claim 3 wherein argon is present at up to about 77% of the total gas flow to the plasma etch chamber.
 5. A method as claimed in claim 1 wherein film temperature is in the range of 100° C. and 170° C.
 6. A method as claimed in claim 1 wherein the chamber pressure is in the range 90 mT to 300 mT.
 7. A method as claimed in claim 1 wherein the power supplied to the plasma is between 700 and 1000 Watts.
 8. A method as claimed in claim 1 wherein the etch is terminated within the film.
 9. A method as claimed in claim 8 wherein the film is within an interconnect structure.
 10. A method as claimed in claim 1 wherein the plasma etch is forming an interconnect structure or other relevant structure in the film.
 11. A device incorporating a film as etched by the method of claim
 1. 